This invention relates to programmable logic array integrated circuit devices (xe2x80x9cprogrammable logic devicesxe2x80x9d or xe2x80x9cPLDsxe2x80x9d), and more particularly to interconnection resources for use on programmable logic devices that increase the speed at which those devices can be made to operate.
Programmable logic devices typically include (1) many regions of programmable logic, and (2) programmable interconnection resources for selectively conveying signals to, from, and/or between those logic regions. Each logic region is programmable to perform any of several different, relatively simple logic functions. The interconnection resources are programmable to allow the logic regions to work together to perform much more complex logic functions than can be performed by any individual logic region. Examples of known PLDs are shown in Wahlstrom U.S. Pat. No. 3,473,160, Freeman U.S. patent Re. 34,363, Cliff et al. U.S. Pat. No. 5,689,195, Cliff et al. U.S. Pat. No. 5,909,126, and Jefferson et al. U.S. Pat. No. 5,215,326, all which are hereby incorporated by reference herein.
A frequent objective in the design of PLDs is to increase the speed at which the device can be operated. The speeds at which signals can travel through the interconnection resources between logic regions is particularly important to determining device speed. Overall, the interconnection resources must have the general-purpose capability of connecting any logic region to any other logic region. But in addition to this, it can be helpful to find ways to make faster interconnections between nearby logic regions. Many complex logic tasks can be broken down into parts, each of which can be performed by a respective cluster of logic regions. By providing interconnection resources that facilitate the flexible formation of clusters of logic regions with high-speed interconnection capabilities among the logic regions in such clusters, the ability of the PLD to perform various complex logic tasks at high speed in enhanced.
In view of the foregoing, it is an object of this invention to provide improved interconnection resources for programmable logic devices.
It is a more particular object of this invention to provide interconnection resources for programmable logic devices that facilitate the formation of extended clusters of nearby logic modules between which high-speed interconnections can be made.
These and other objects of the invention are accomplished in accordance with the principles of the invention by providing programmable logic devices with interconnection resources that facilitate the provision of interconnections between logic modules in adjacent rows of logic regions, as well as between nearby logic regions in each row. Typically the logic regions on a PLD are arranged in a two-dimensional array of intersecting rows and columns of such regions. Each logic region may include a plurality of subregions. Local feedback conductors may be provided for facilitating communication among the subregions in a region. In addition, these local feedback conductors may be interleaved between horizontally adjacent regions in a row, thereby facilitating high speed interconnection among the subregions of horizontally adjacent regions. In accordance with this invention such high speed local interconnection is additionally provided between adjacent rows in any of several ways. For example, output signals of subregions in each row may be additionally applied substantially directly (i.e., without making use of the more general-purpose interconnection resources of the device) to programmable logic connectors (e.g., multiplexers) feeding output drivers that are otherwise normally or nominally associated with subregions in an adjacent row. This makes it possible for the subregions in one row to optionally drive interconnection resources that are normally associated with an adjacent row, thereby facilitating clustering of logic regions in adjacent rows. As an alternative or addition to the foregoing, the interconnection resources that bring signals into the regions in each row can be partly shifted or extended relative to the rows so that some signals can be more readily and directly brought into each row from the adjacent rows, again without having to make use of the more general-purpose interconnection resources of the device. This again facilitates forming clusters of logic regions in adjacent rows. As still another alternative, the interconnection resources that bring signals into each row can be substantially directly driven by signals from similar resources in another row, thereby again facilitating the formation of clusters of logic regions in adjacent rows without needing to use the general-purpose interconnection resources.
As an alternative or addition to the foregoing, clustering of logic regions along a row may be facilitated by providing conductors associated with each logic region that extend adjacent a relatively small sub plurality of the other adjacent logic regions in that row. For example, one of these conductors associated with each logic region may extend to the left from that logic region adjacent a relatively small number of other logic regions to the left of the associated logic region, and another of these conductors may extend to the right by approximately the same number of other logic regions. The same signal or different signals from the associated logic region can be applied to each of these conductors, and thereby to the other logic regions that these conductors are adjacent to. (The signals on these conductors can alternatively come from other sources.) The relatively short length, light loading, and other similar characteristics of these conductors make them especially suitable for use in providing high-speed interconnections from the associated logic region (or other signal source(s)) to the other logic regions that they are adjacent to, thereby again facilitating flexible clustering of nearby logic regions.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.